The present invention relates to a mask-less method of differentially chemically etching the surfaces of recess-patterned copper-based films or layers for providing at least partial planarization thereof. More particularly, the present invention relates to a method for forming a layer of copper or copper-based alloy filling a plurality of spaced apart recesses formed in the surface of a substrate, wherein the exposed upper surface of the layer is substantially coplanar with non-recessed areas of the substrate. Even more particularly, the present invention relates to a method for performing xe2x80x9cback-endxe2x80x9d metallization of semiconductor high-speed integrated circuit devices having submicron design features and high conductivity interconnect features, which method facilitates full planarization of the metallized surface by chemical-mechanical polishing (CMP), increases manufacturing throughput, and reduces fabrication cost.
The present invention relates to a mask-less differential chemical etching method useful in processing copper or copper-based films as part of metallization processing of particular utility in integrated circuit semiconductor device and circuit board manufacture, and is especially adapted for use in processing employing xe2x80x9cdamascenexe2x80x9d (or xe2x80x9cin-laidxe2x80x9d) technology.
The escalating requirements for high density and performance associated with ultra large-scale integration (ULSI) semiconductor device wiring are difficult to satisfy in terms of providing submicron-sized (e.g., below 0.18 xcexcm), low RC time constant metallization patterns, particularly wherein the submicron-sized metallization features such as vias, contact areas, grooves, trenches, etc., have high aspect (i.e., depth-to-width) ratios due to microminiaturization.
Semiconductor-devices of the type contemplated herein typically comprise a semiconductor wafer substrate, usually of doped monocrystalline silicon, and a plurality of sequentially formed dielectric interlayers and conductive patterns formed therein and/or therebetween. An integrated circuit is formed therefrom containing a plurality of patterns of conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of vertically spaced apart metallization layers are electrically interconnected by a vertically oriented conductive plug filling a via hole formed in the dielectric layer separating the layers, while another conductive plug filling a contact area hole establishes electrical contact with an active region, such as a source/drain region, formed in or on the semiconductor substrate. Conductive lines formed in groove or trench-like openings in overlying dielectric layers extend substantially parallel to the semiconductor substrate. Semiconductor devices of such type fabricated according to current technology may comprise five or more levels of such metallization in order to satisfy device geometry and miniaturization requirements.
Electrically conductive films or layers of the type contemplated herein for use in e.g., xe2x80x9cbackend-endxe2x80x9d semiconductor manufacturing technology as required for fabrication of devices as above described typically comprise a metal such as titanium, tungsten, aluminum, chromium, nickel, cobalt, silver, gold, copper, and their alloys. In use, each of the recited metals presents advantages as well as drawbacks. For example, aluminum (Al) is relatively inexpensive, exhibits low resistivity, and is relatively easy to etch. However, in addition to being difficult to deposit by lower cost, lower temperature, more rapid xe2x80x9cwetxe2x80x9d technology processes such as electrodeposition, step coverage with aluminum is poor when the metallization features are scaled down to submicron size, resulting in decreased reliability of interconnections, high current densities at certain locations, and increased electromigration. In addition, low dielectric constant (xe2x80x9clow kxe2x80x9d) materials, e.g., polyamides, when employed as dielectric interlayers, create moisture/bias reliability problems when in contact with aluminum.
The use of via-plugs filled with tungsten (W) may alleviate several of the above-described problems/drawbacks associated with aluminum. However, most W-based processes are complex and expensive, primarily due to the refractory nature of W. In addition, the relatively high resistivity of W may cause high Joule heating which can undesirably enhance electromigration of aluminum in adjacent wiring. Moreover, W plugs are susceptible to void formation therein and high contact resistance at the interface with the aluminum wiring layer.
Copper (Cu) and Cu-based alloys are particularly attractive for use in large-scale integration (LSI), very large-scale integration (VLSI), and ultra large-scale integration (ULSI) devices requiring multi-level metallization systems for xe2x80x9cback-endxe2x80x9d processing of the semiconductor wafers on which the devices are based. Cu and Cu-based metallization systems have very low resistivities, i.e., significantly lower than that of W and even lower than those of previously preferred systems utilizing Al or Al-based alloys, as well as significantly higher resistance to electromigration. Moreover, copper and its alloys enjoy a considerable cost advantage over a number of the above-enumerated metals, notably silver and gold. Also, in contrast to Al and the refractory type metals such as W, Ti and Ta, copper and its alloys can be readily deposited at low temperatures in good quality, bright layer form by well-known electroplating techniques, at deposition rates fully compatible with the requirements of device manufacturing throughput.
In addition to convenient, relatively low cost, low temperature, high manufacturing throughput xe2x80x9cwetxe2x80x9d deposition by electroplating, copper and its alloys are readily amenable to low-cost, high throughput xe2x80x9cwetxe2x80x9d deposition by xe2x80x9celectrolessxe2x80x9d plating of high quality films for efficiently filling recesses such as vias, contact areas, grooves, and trenches forming interconnection routing. Such electroless plating generally involves the controlled autocatalytic deposition of a film of copper or an alloy thereof on a catalytic surface by interaction with a solution containing at least a copper salt and a chemical reducing agent, whereas electroplating comprises employing electrons supplied to an electrode (i.e., the semiconductor wafer) from an external source (i.e., power supply) for reducing copper ions in solution and depositing the reduced metal atoms obtained thereby on the electrode surface. In either case, a nucleation/seed layer is required for catalytic/deposition (as in electroless plating) or electrolytic deposition (as in electroplating) on the types of substrates contemplated for use herein. Finally, while electroplating requires a continuous nucleation/seed layer, very thin and discontinuous islands of a catalytic metal may be employed with electroless plating.
As indicated above, a commonly employed method for forming xe2x80x9cinlaidxe2x80x9d metallization patterns such as are required for xe2x80x9cback-endxe2x80x9d metallization processing of semiconductor wafers employs xe2x80x9cdamascenexe2x80x9d type technology. Generally, in such processing methodology, a recess (i.e., an opening, irrespective of shape or geometry) for forming, e.g., a via hole in a dielectric interlayer, for electrically connecting vertically separated metallization layers, is created in the dielectric interlayer by conventional photolithographic masking and etching techniques, and filled with a metal plug, typically of tungsten. Any excess conductive material (e.g., tungsten) on the surface of the dielectric interlayer is then removed by, e.g., chemical-mechanical polishing (xe2x80x9cCMPxe2x80x9d) techniques, wherein a moving pad is biased against the surface to be polished, with the interposition of a slurry containing finely-dimensioned abrasive particles (and other ingredients) therebetween. As a result of the CMP processing, the surface of the metal plug filling the recess is coplanar with the surface of the adjacent, non-recessed surface area of the dielectric interlayer.
A variant of the above-described technique, termed xe2x80x9cdual-damascenexe2x80x9d processing, involves the formation of an opening comprising a lower contact or via hole section in communication with an upper groove or trench section, which opening is filled with a conductive material, typically a metal, to simultaneously form a conductive plug in electrical contact with a conductive line.
Referring now to FIG. 1, schematically shown therein in simplified cross-sectional view are the major steps in a conventional damascene processing sequence employing relatively low cost, low temperature, high manufacturing throughput copper or copper-based electroplating and CMP techniques for forming recessed xe2x80x9cback-endxe2x80x9d metallization patterns in a semiconductor device formed in or on a semiconductor wafer substrate 1. In a first step (shown in the uppermost drawing), the desired arrangement or pattern of conductors is initially defined as an arrangement or pattern of recesses 2 such as holes, grooves, trenches, etc., formed (as by conventional photolithographic masking and etching techniques) in the surface 4 of a dielectric layer 3 (e.g., a silicon oxide and/or nitride or an organic polymeric material) deposited or otherwise formed over the semiconductor substrate 1. In a second step (shown in the middle drawing), a layer 5 of copper or copper-based alloy is deposited by conventional electroplating techniques to fill the recesses 2. In order to ensure complete filling of the recesses 2, the copper or copper-based layer 5 is deposited as a relatively thick blanket (or xe2x80x9coverburdenxe2x80x9d) layer of excess thickness t (measured from the non-recessed upper surface 4 of the dielectric layer 3) so as to overfill the recesses 2 and cover the entire upper surface area 4 of the dielectric layer 3. In the next step (shown in the lowermost drawing), the entire excess thickness t of the metal overburden layer 5 over the surface 4 of the dielectric layer 3 is removed by a CMP process utilizing an alumina-based slurry, leaving metal portions 5xe2x80x2 in the recesses 2 with their exposed upper surfaces 6 substantially coplanar with the non-recessed surfaces 4 of the dielectric layer 3.
The above-described conventional damascene process forms in-laid conductors 5xe2x80x2 in the dielectric layer 3 while avoiding problems associated with other types of metallization patterning processing, e.g., blanket metal layer deposition, followed by photolithographic masking and etching and dielectric gap filling. In addition, such single or dual damascene-type processing can be performed with a variety of other types of substrates, e.g., printed circuit boards, with and/or without intervening dielectric layers, and with a plurality of metallization levels, i.e., five or more levels.
However, the use of electroplated copper or copper-based xe2x80x9cback-endxe2x80x9d metallization as described above has presented a number of problems. For example, the deposited copper or copper-based alloys have a significant tendency to diffuse into the underlying semiconductor substrate material, typically silicon (Si), resulting in degradation of its semiconductive properties (e.g., diffusion lengths, carrier lifetimes, etc.), as well as poor adhesion to various materials employed as dielectric interlayers, etc. As a consequence of these phenomena associated with copper-based metallurgy, it is generally necessary to provide an adhesion promoting and/or diffusion barrier layer intermediate the semiconductor substrate and the overlying copper-based metallization layer. Suitable materials for such diffusion/barrier layer include, but are not limited to, e.g., chromium, tantalum, and tantalum nitride. Any nucleation/seed layer necessary for catalyzing electroless copper deposition or supplying electrons for copper electrodeposition thereon is deposited atop the diffusion/barrier layer. Suitable materials for such nucleation/seed layer include, but are not limited to, e.g., copper or copper-based alloys and refractory metals such as titanium, tantalum, tungsten, etc.
Another drawback associated with electroplated copper or copper-based metallization, vis-a-vis metallization by physical or chemical vapor deposition techniques, is the tendency for ridge build-up over sharp comers of vias, grooves, and trenches. Thus, as previously indicated, in conventional practices utilizing electrolytic deposition of copper or copper-based conductors, a rather thick blanket or overburden layer 5, of thickness t, typically about 0.5-1.5 xcexcm, must be deposited over the recess patterned surface of the dielectric layer 3 to ensure complete filling (i.e., overfilling) of recesses 2 such as via holes, trenches, grooves, and other variously configured openings. Moreover, the resulting surface after overfilling may be highly non-planar, with the layer thicknesses t thereof (measured from the non-recessed surface 4 of the dielectric layer 3) spanning a significant portion of the above-described range of thicknesses. More specifically, and with particular reference to the middle drawing of FIG. 1, the upper surface 7 of the relatively thick electroplated copper or copper-based overburden layer 5 includes a pattern of depressions (i.e., recesses) 2xe2x80x2 which substantially replicates and is in vertical registry with the pattern of recesses 2 formed in the underlying dielectric layer 3.
Removal of such thick, non-planar blanket or overburden layers of copper or copper-based alloy in the subsequent CMP step for planarizing the interconnection metallization entails a number of disadvantages. For example, removal of the excess copper or copper-based alloy material by CMP is slow and expensive. Specifically, typical copper or copper alloy removal rates by CMP employing a conventional alumina-based slurry are on the order of about 2,000-3,000 xc3x85/min. Consequently, removal of 0.5-1.5 xcexcm thick copper-based layers can require long processing times extending up to about 5 minutes, considerably longer than that desired for good manufacturing throughput and reduced expense. In addition, removal of such thick as-deposited copper or copper-based blanket or overburden layers by CMP results in less uniform polished layers as are obtained when CMP is performed on thinner blanket or overburden layers. Such poor uniformity is generally accompanied by an increase in defects such as non-planarity (xe2x80x9cdishingxe2x80x9d) and gouging (xe2x80x9cerosionxe2x80x9d) between adjacent metallization lines. Yet another drawback associated with CMP of such thick overburden layers is the requirement for treatment of large volumes of waste slurry containing abrasive particles and environmentally hazardous substances such as copper ions arising from abrasion and dissolution of the copper or copper-based alloy layers during CMP processing. Finally, environmentally acceptable disposal of solid sludge containing the abrasive particles and copper ions resulting from such waste slurry treatment is difficult and expensive.
Thus, there exists a need for a method for forming in-laid electroplated copper or copper-based metallization patterns by a damascene technique which does not suffer from the problems of the conventional art, i.e., reduced manufacturing throughput, increased cost, poor uniformity, increased occurrence of defects such as xe2x80x9cdishingxe2x80x9d and xe2x80x9cgougingxe2x80x9d, generation and requirement for treatment of large amounts of CMP waste slurry and sludge resulting therefrom, etc., arising from the CMP processing of thick blanket or overburden layers characteristic of copper or copper-based electroplating of recess-patterned substrates. Specifically, there exists a need for an improved electroplating and CMP-based metallization method for forming copper or copper-based xe2x80x9cback-endxe2x80x9d in-laid contacts and interconnection routing of active regions (e.g., transistors, diodes, etc.) and components in integrated circuit semiconductor devices. Moreover, there exists a need for an improved CMP-based method for forming such contacts, vias, and interconnect routings which is fully compatible with conventional process flow and methodology in the manufacture of such integrated circuit semiconductor devices and other devices requiring in-laid metallization patterns, e.g., circuit boards.
The present invention addresses and solves the above-described problems and drawbacks attendant upon conventional processes for manufacturing semiconductor devices utilizing electroplated copper or copper-based metallization, particularly in the reduction of the thickness of the electroplated blanket or overburden layer required to be removed by CMP processing in the formation of in-laid xe2x80x9cback-endxe2x80x9d contacts/metallization patterns by damascene techniques, thereby obtaining good manufacturing throughput and improved product quality.
An advantage of the present invention is a mask-less method for differentially etching a recess-patterned surface of a layer of copper or copper-based alloy.
Another advantage of the present invention is an abrasive-less, chemical method for at least partially planarizing a recess-patterned surface of a layer of copper or copper-based alloy.
Still another advantage of the present invention is a method of manufacturing a device with an in-laid copper or copper-based metallization pattern at lower cost and with higher manufacturing throughput than with conventional process methodology.
Yet another advantage of the present invention is a method of manufacturing an integrated circuit semiconductor device utilizing copper or copper-based xe2x80x9cback-endxe2x80x9d in-laid contacts and interconnections by a damascene process, with greater uniformity and planarity, improved product quality, and reduced defects.
A further advantage of the present invention is a method for forming electroplated copper or copper-based in-laid contacts by CMP at an increased speed, lower cost, and with greater planarity than obtainable with conventional CMP-based processes.
A yet further advantage of the present invention is an improved method for forming copper or copper-based in-laid contacts and metallization patterns by a damascene type CMP-based process which is fully compatible with existing process methodology.
A still further advantage of the present invention is an improved copper etchant solution for differentially etching recess-patterned surfaces of copper or copper-based layers.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to one aspect of the present invention, the foregoing and other advantages are achieved in part by a method of mask-less differential etching/planarizing a recess-patterned surface of copper or copper alloy, which method comprises the sequential steps of:
(a) providing a workpiece having upper and lower opposed major surfaces, the upper major surface comprising a layer of copper or a copper alloy and including a recessed area and a non-recessed area;
(b) securing the lower major surface of the workpiece to a facing surface of a movable workpiece holder for providing movement of the workpiece in a direction parallel to the upper surface thereof;
(c) providing a source of a liquid etchant solution, the liquid etchant solution comprising:
i. a copper or copper alloy etchant;
ii. a surfactant in an amount sufficient for providing wetting of the copper or copper alloy surface by the etchant solution;
iii. an additive in an amount sufficient for increasing the viscosity of the etchant solution to a preselected level greater than that of the solvent; and
iv. a liquid solvent;
(d) directing etchant solution from the source onto the upper surface of the workpiece while moving the workpiece in a direction parallel to the upper surface, thereby at least partially filling the recessed area with etchant solution and distributing the etchant solution as a film covering the non-recessed area, the film of etchant solution being replenished with fresh etchant solution from the source at a faster rate than the etchant solution filling the recessed area; whereby the rate of etching of the copper or copper alloy within the recessed area is slower than that of the non-recessed area, resulting in differential etching of the recess-patterned surface of the layer of copper or copper alloy; and
(e) continuing the differential etching of step (d) for a time sufficient to reduce the thickness of the non-recessed area of the copper or copper alloy layer to a preselected thickness, thereby at least partially planarizing the upper surface.
In embodiments according to the invention, the etchant solution is provided as an aqueous solution at a temperature of about 20-50xc2x0 C. and comprising:
i. a copper or copper alloy etchant comprising about 10 to about 20% hydrogen peroxide (H2O2) and about 0.2 to about 2% of an organic acid selected from the group consisting of citric acid, oxalic acid, and phthalic acid;
ii. a water-soluble surfactant selected from the group consisting of cationic, anionic, non-ionic, and bi-polar surfactants, in an amount sufficient for providing the desired wetting, such that etchant solution fills the recessed area and aids in retaining the etchant solution therein during workpiece motion;
iii. a water-soluble monomeric or polymeric glycol selected from the group consisting of ethylene glycols, propylene glycols, glycerols, polyethylene glycols, and polypropylene glycols, in an amount sufficient to provide the solution with a preselected viscosity greater than that of water at the same temperature, whereby loss of etchant solution flowing outwardly from the recessed area during workpiece motion is reduced; and
iv. balance water as solvent.
According to embodiments of the present invention, the workpiece is provided with rotational, oscillatory, or orbital motion during step (b). In the case of rotational motion, the workpiece is rotated around a central axis perpendicular to the upper surface at at least 1,000 rpm.
In preferred embodiments according to the present invention, the upper surface of the copper or copper alloy layer comprises a patterned plurality of spaced apart recessed areas of different widths and/or depths, with non-recessed areas therebetween, and the workpiece further comprises a semiconductor wafer substrate having a dielectric layer thereon and underlying the copper or copper alloy layer, the patterned plurality of recesses in the copper or copper alloy layer being in vertical registry with a corresponding patterned plurality of recesses of different widths and/or depths formed in the underlying dielectric layer, the latter-mentioned plurality of recesses forming electrical contact areas, vias, interlevel metallization, and/or interconnection routing of at least one active device region or component of the semiconductor wafer.
In further preferred embodiments according to the present invention, the semiconductor wafer substrate comprises silicon and an adhesion promoting and/or diffusion barrier layer selected from chromium, tantalum, and tantalum nitride is provided at interfaces between the dielectric layer and the copper or copper alloy layer.
According to yet another preferred embodiment, the inventive method comprises the further step (f) of substantially fully planarizing the differentially etched upper surface of step (e) by chemical-mechanical polishing (CMP), as by the use of an alumina-based slurry.
According to another aspect of the invention, a method of manufacturing a semiconductor device comprises the sequential steps of:
(a) providing a substrate comprising a semiconductor wafer having formed thereon a dielectric layer having a surface comprising a recessed area and a non-recessed area;
(b) depositing, by electroplating, a layer of copper or copper alloy over the surface of the dielectric layer, the copper or copper alloy layer overfilling the recessed area and including a blanket or overburden layer covering the non-recessed area to a preselected first thickness, the surface of the copper or copper alloy layer including a recessed area and a non-recessed area in substantial vertical registry with corresponding ones of the underlying dielectric layer;
(c) reducing the thickness of the blanket or overburden layer by a mask-less, differential chemical etching process to a second thickness; and
(d) chemical-mechanical polishing the remaining second thickness of the blanket or overburden layer to (1) substantially remove same from the surface of the non-recessed area of the dielectric layer and (2) render the exposed upper surface of the portion of the copper or copper alloy layer filling the recessed area of the dielectric layer substantially coplanar with the surface of the non-recessed area of the dielectric layer.
In embodiments according to the invention, the semiconductor substrate comprises a silicon wafer having upper and lower opposed major surfaces; the dielectric layer is formed on the upper major surface and includes a patterned surface comprising a plurality of spaced apart recessed areas with non-recessed surface areas therebetween; the copper or copper alloy layer is electroplated over the patterned surface so as to overfill each of the recessed areas and to cover each of the non-recessed areas with the blanket or overburden layer, the surface of the copper or copper alloy layer including a pattern of recessed areas with non-recessed surface areas therebetween in substantial vertical registry with the corresponding pattern of recessed areas and non-recessed areas of the underlying dielectric layer; the lower major surface of the wafer is secured to a facing surface of a movable wafer holder for moving the wafer in a direction parallel to the upper surface thereof; a source of a liquid etchant solution is provided, the liquid etchant solution comprising a copper or copper alloy etchant, a surfactant in an amount sufficient for providing wetting of the copper or copper alloy surface by the etchant solution, an additive in an amount sufficient for increasing the viscosity of the etchant solution to a preselected level greater than that of the solvent, and a liquid solvent; the etchant solution from said source is directed onto the upper surface of the wafer while moving the wafer in a direction parallel to the upper surface (as by rotating at at at least 1,000 rpm about a central axis perpendicular to the upper surface), thereby at least partially filling each of the plurality of recessed areas with etchant solution and distributing the etchant solution as a film covering the non-recessed areas, the film of etchant solution being replenished with fresh etchant solution from the source at a faster rate than the etchant solution filling the recessed areas, whereby the rate of etching of the copper or copper alloy within the recessed areas is slower than that of the non-recessed areas, resulting in differential etching of the recess-patterned surface of the layer of copper or copper alloy; continuing the differential etching for a time sufficient to reduce the first thickness of the blanket or overburden layer to the preselected second thickness; and performing CMP of the remaining second thickness (as by use of an alumina-based abrasive slurry) of the blanket or overburden layer to substantially remove same from the surfaces of the non-recessed areas of the dielectric layer and render the exposed upper surfaces of the copper or copper alloy layer portions filling the recessed areas of the dielectric layer substantially coplanar with the non-recessed surface areas of the dielectric layer.
In further embodiments according to the present invention, the plurality of recessed areas of the dielectric area are provided with different widths and/or depths for forming electrical contact areas, vias, interlevel metallization, and/or interconnection routing of at least one active device region or component of the wafer; the dielectric layer is provided with an adhesion promoting and/or diffusion barrier layer selected from chromium, tantalum, and tantalum nitride and and an overlying nucleation/seed layer selected from refractory metals, copper, and copper-based alloys prior to electroplating of the copper or copper alloy layer thereon; the preselected first thickness of the copper or copper alloy blanket or overburden layer is from about 0.5 xcexcm to about 1.5 xcexcm, and the preselected second thickness thereof after differential etching is less than about 5,000 xc3x85.
According to yet another aspect according to the present invention, a liquid etchant solution for use in mask-less differential etching of recess-patterned copper or copper alloy layers comprises:
i. a copper or copper alloy etchant;
ii. a surfactant in an amount sufficient for providing wetting of copper or copper alloy surfaces by the etchant solution;
iii. an additive in an amount sufficient for increasing the viscosity of the etchant solution to a preselected level greater than that of the solvent; and
iv. a liquid solvent.
In embodiments according to the invention, the copper or copper alloy etchant comprises about 10 to about 20% hydrogen peroxide (H2O2) and about 0.2 to about 2% of an organic acid selected from citric acid, oxalic acid, and phthalic acid; the surfactant is water-soluble, is selected from cationic, anionic, non-ionic, and bi-polar surfactants, and is present in an amount such that the solution wets and fills recesses in the surface of the copper or copper alloy; the additive is water-soluble, comprises a monomeric or polymeric glycol selected from ethylene glycols, propylene glycerols, polyethylene glycols, and polypropylene glycols, and is present in an amount sufficient to provide the solution with a viscosity greater than that of water at the same temperature, whereby loss of etchant solution from recessed areas of the copper or copper alloy layer during motion thereof is reduced; and balance water as solvent.
According to still another aspect according to the present invention, silicon semiconductor integrated circuit devices comprising copper or copper-based xe2x80x9cback-endxe2x80x9d metallization patterns formed by the inventive method are provided.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will be described and become apparent, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.